1. Field of the Invention
The present invention generally relates to manufacturing methods of semiconductor packages. More specifically, the present invention relates to a manufacturing method of a semiconductor package, the semiconductor package having a semiconductor chip and a wiring structural body electrically connected to the semiconductor chip.
2. Description of the Related Art
Conventionally, a semiconductor package where a semiconductor chip is mounted on a multi-layer wiring board via a solder bump or the like has been known. An example of a related art semiconductor package is discussed with reference to FIG. 1 through FIG. 3.
FIG. 1 is a cross-sectional view of an example of a related art semiconductor package. As illustrated in FIG. 1, a semiconductor package 100 has a structure where a semiconductor chip 200 is mounted on a substantially center part of a multi-layer wiring board 300 via bumps 400 and is sealed by underfill resin 500. Voids 700 are generated in the underfill resin 500.
The semiconductor chip 200 includes a semiconductor substrate 210 and electrode pads 220. The semiconductor substrate 210 has a structure where a semiconductor integrated circuit (not illustrated in FIG. 1) is formed on a substrate made of, for example, silicon (Si) or the like. The electrode pads 220 are formed at one side of the semiconductor substrate 210 and electrically connected to the semiconductor integrated circuit (not illustrated in FIG. 1).
The multi-layer wiring board 300 has a structure where a first wiring layer 310, a first insulation layer 340, a second wiring layer 320, a second insulation layer 350, a third wiring layer 330, and a solder resist layer 360 are stacked in order. The first wiring layer 310 and the second wiring layer 320 are electrically connected to each other via first via holes 340x provided in the first insulation layer 340. The second wiring layer 320 and the third wiring layer 330 are electrically connected to each other via second via holes 350x provided in the second insulation layer 350. External connection terminals 370 are formed on the third wiring layer 330 exposed in opening parts 360x of the solder resist layer 360. The first wiring layer 310 works as electrode pads to be connected to the electrode pads 220 of the semiconductor chip 200. The external connection terminals 370 work as terminals to be connected to a motherboard or the like.
The first wiring layer 310 of the multi-layer wiring board 300 and the electrode pads 220 of the semiconductor chip 200 are electrically connected to each other via the solder bumps 400. The underfill resin 500 is supplied between surfaces of the semiconductor chip 200 and the multi-layer wiring board 300 facing each other.
Next, a manufacturing method of the related art semiconductor package is discussed with reference to FIG. 2 and FIG. 3. FIG. 2 is a first view showing an example of a manufacturing process of the related art semiconductor package 100. FIG. 3 is a second view showing the example of the manufacturing process of the related art semiconductor package. In FIG. 2 and FIG. 3, parts that are the same as the parts illustrated in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
First, in a step illustrated in FIG. 2, the semiconductor chip 200 and the multi-layer wiring board 300 manufactured by a known method are prepared. Then, pre-solder 410 is formed on the electrode pads 220 of the semiconductor chip 200. In addition, pre-solder 420 is formed on the first wiring layer 310 of the multi-layer wiring board 300 and flux 600 is applied so as to cover the pre-solder 420. The semiconductor chip 200 has a designated small thickness such as approximately 300 μm.
Next, in a step illustrated in FIG. 3, the first wiring layer 310 side of the multi-layer wiring board 300 and the electrode pads 220 side of the semiconductor chip 200 are made to face each other so that positions of the pre-solder 410 and positions of the pre-solder 420 correspond to each other. In addition, the pre-solder 410 and the pre-solder 420 are heated at, for example, approximately 230° C. so that solders are made molten and the solder bumps 400 are formed. In addition, the flux 600 is removed. The flux 600 may not be completely removed by cleaning so that residual 600A may remain.
Next, in a structural body illustrated at a lower side of FIG. 3, by supplying the underfill resin 500 between the surfaces of the semiconductor chip 200 and the multi-layer wiring board 300 facing each other, the semiconductor package 100 illustrated in FIG. 1 is completed. In this case, since a distance between the surfaces of the semiconductor chip 200 and the multi-layer wiring board 300 facing each other is short such as approximately 50 μm, it may be difficult for a liquid underfill material to flow and therefore the voids 700 may be generated. See International Patent Application Publication Official Gazette No. 02/15266 and International Patent Application Publication Official Gazette No. 02/33751.
However, while the coefficient of thermal expansion of the semiconductor chip 200 is, for example, approximately 3 ppm/° C., the coefficient of thermal expansion of the multi-layer wiring board 300 is, for example, approximately several tens ppm/° C. When the pre-solder 410 and the pre-solder 420 are heated in a step illustrated in FIG. 3, due to such a difference of the coefficients of thermal expansion between the semiconductor chip 200 and the multi-layer wiring board 300, while the semiconductor chip 200 may not be deformed, the multi-layer wiring board 30 may be warped in a convex or undulated manner. Because of this, a position shift between the semiconductor chip 200 and the multi-layer wiring board 300 may be generated so that connecting reliability between the semiconductor chip 200 and the multi-layer wiring board 300 may be degraded.
In addition, in the step illustrated in FIG. 3, if the residual 600A of the flux 600 remains, insulation failure may be generated, so that the connecting reliability between the semiconductor chip 200 and the multi-layer wiring board 300 may be degraded.
In addition, in a case where the distance between the surfaces of the semiconductor chip 200 and the multi-layer wiring board 300 facing each other is short, it is difficult for the liquid underfill material to flow so that the voids 700 may be generated.